Memory bandwidth is a key factor in the performance of modern gaming systems and has increased with each new generation largely through increases in signaling rate and input/output (I/O) pins. Unfortunately, pin count and signaling rate are beginning to approach physical limits so that further increases must overcome difficult challenges and will likely be unable to keep pace with the increased memory bandwidth demanded by next-generation systems.
One alternative to increasing pin count or signaling rate is to add additional graphics controllers to achieve increased parallel processing within a graphics pipeline. Unfortunately, many of the data structures that need to be accessed to carry out the functions within the graphics pipeline tend to be shared so that, even if multiple graphics controllers are provided, a performance penalty is typically incurred each time two controllers contend for a shared data structure, as one of the controllers generally must wait for the other to finish accessing the memory in which the shared data structure is stored.